1. Field
Example embodiments may relate to methods of fabricating semiconductor devices, for example, to methods of fabricating image sensors.
2. Conventional Art
An image sensor may be a semiconductor device to convert an optical image to an electrical signal. FIG. 1 is a block diagram depicting a conventional image sensor, for example, a CMOS image sensor. Referring to FIG. 1, the conventional CMOS image sensor may include a pixel array region to transmit an optical signal and a logic region for realizing an image. For example, the logic region may control or process the optical signal to realize the image. For example, the optical signal may be a signal comprising information regarding the image.
The pixel array region may include a plurality of unit pixels arranged in arrays. Each of the unit pixels may include a photo-diode (or alternatively, a photo-sensitive device) to detect an optical signal and transmitting devices for transmitting an electrical signal based on the optical signal. The logic region may include a capacitor block to store analog signals, an analog digital converter (ADC) block to transform the analog signals to digital signals, a decoder/driver block to select unit pixels, and a control register block.
According to a method of fabricating a conventional image sensor, to form a capacitor structure in the capacitor block, a contact structure connected to a lower electrode may be formed after a lower electrode, a dielectric layer, and an upper electrode are formed. If the upper electrode is formed in a hole or in a trench of an interlayer insulating layer, an additional planarizing process may be required to planarize the upper electrode, and to form a contact plug for the contact structure. Furthermore, further additional processes to form contact structures connected to transistors in other logic regions may be required.
U.S. Pat. No. 6,239,010 by Jau-Hone Lu discloses a method of manufacturing a wiring structure that connects an upper electrode of a capacitor and a wiring structure that connects a gate electrode, simultaneously. However, the method may also require additional processes for forming the contact structure connected to the lower electrode of the capacitor. Moreover, after the contact plug is formed, a trench in a capacitor portion may remain unfilled. Therefore, further planarizing processes may be required.
Additionally, this structure includes metal silicide in the gate electrode and the lower electrode, which may be a drawback. For example, if the structure is applied to an image sensor, an additional photolithography and etching process may be required to remove the metal silicide in the pixel array region to reduce dark defects and noise in the pixel array region.